Charging the substrate of some CMOS or MOS devices to a negative potential has several advantages over a grounded substrate. It lowers the variation of the threshold voltages due to the body effect, increases punch-through voltages, and lowers the diffusion-substrate capacitance (i.e. junction capacitance) without requiring a decrease in the substrate doping. It also protects the chip from forward biasing the substrate due to voltage undershoots at the inputs.